`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/05/06 00:08:05
// Design Name: 
// Module Name: test_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module test_tb(

    );

logic ACLK;
logic ARESETn;
//
logic ARVALID;
logic [31:0] ARADDR;
logic [7:0] ARLEN;
logic ARREADY;
logic [31:0] RDATA;
logic RLAST;
logic RREADY;
logic [1:0] RRESP;
//
initial
begin
    ACLK=0;
	forever
	   #5 ACLK=~ACLK;
end
//
initial
begin
   ARESETn=0;
   #100
   ARESETn=1;
end
//inst	
axi_master U1(
.ACLK(ACLK),
.ARESETn(ARESETn),
//
.ARVALID(ARVALID),
.ARADDR(ARADDR),
.ARLEN(ARLEN),
.ARREADY(ARREADY),
//
.RDATA(RDATA),
.RVALID(RVALID),
.RLAST(RLAST),
.RRESP(RRESP),
.RREADY(RREADY)
);
//
axi_slave U2(
.ACLK(ACLK),
.ARESETn(ARESETn),
//
.ARVALID(ARVALID),
.ARADDR(ARADDR),
.ARLEN(ARLEN),
.ARREADY(ARREADY),
//
.RDATA(RDATA),
.RVALID(RVALID),
.RLAST(RLAST),
.RRESP(RRESP),
.RREADY(RREADY)
);

endmodule
